1. Field of the Invention
The invention relates to a method of fabricating semiconductor memory devices employing floating gates, and more particularly, to a method of fabricating NAND type memory devices employing floating gates having improved coupling ratio.
2. Description of the Prior Art
One class of semiconductor memory devices employ floating gates; that is, gates which are completely surrounded by an insulating layer, such as a silicon oxide. The presence or absence of charge in the floating gates represents binary information. These are called electrically programmable read only memories (EPROM). EEPROMs are erasable electrically programmable read only memories. "Flash" memory devices are those in which all of the cells can be erased in a single operation. As noted in the paper, "A 4-Mb NAND EEPROM with Tight Programmed V.sub.t Distribution," by M. Momodomi et al, IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 492-496, flash EEPROMs are NOR-structured cells in which memory cells are connected to a bit line in a parallel manner. A NAND-structured cell in which memory cells are arranged in series dramatically reduces the number of cell components as well as the cell size.
The two papers, "Technology Trend of Flash-EEPROM-Can Flash-EEPROM overcome DRAM?," by Fujio Masuoka, 1992 Symposium on VLSI Technology Digest of Technical Papers, pp. 6-9 and "A 1.13 um.sup.2 Memory Cell Technology for Reliable 3.3 V 64M NAND EEPROMs," by S. Aritome et al, Extended Abstracts of the 1993 International Conference on Solid State Devices and Materials, pp. 446-448 discuss the future of NAND type EEPROMs. The coupling ratio of the NAND type EEPROM is limited, so the floating gate must overlap the field oxide area to improve the coupling ratio or the cell size must be increased or a higher program voltage used.
A number of workers in the art have described improved designs for NAND type EEPROMs. U.S. Pat. No. 5,094,971 to Kanebako teaches miniaturizing NAND type ROMs by self-aligned ion implantation. U.S. Pat. No. 5,273,923 to Chang et al teaches forming a tunneling window which overlaps both the active region and the field isolation region of the memory circuit. U.S. Pat. No. 4,945,068 to Sugaya teaches forming the thin tunnel oxide and the thick gate oxide in a single oxidation step using implanted nitrogen ions to slow the oxidation in the planned tunnel oxide region. U.S. Pat. No. 5,284,786 to Sethi teaches another method of forming a tunnel window.